Selective refresh with software components

ABSTRACT

A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

RELATED APPLICATIONS

This application is a Continuation of U.S. patent Ser. No. 13/975,873,filed Aug. 26, 2013, entitled SELECTIVE REFRESH WITH SOFTWARECOMPONENTS, which claims the benefit of priority under 35 U.S.C. 119(e)to Provisional Application Ser. No. 61/693,911, filed Aug. 28, 2012,entitled SELECTIVE REFRESH WITH SOFTWARE COMPONENTS, which areincorporated by reference in their entirety for all purposes.

TECHNICAL FIELD

The disclosure herein relates to memory systems, and more specificallyto methods and apparatus for memory refresh operations.

BACKGROUND

Memory systems typically employ large amounts of DRAM memory as mainmemory. At the transistor level, a DRAM cell is a capacitor structure,with the capability of maintaining a charge representing a “bit” on theorder of approximately 64 mS. To maintain the charge, the cell needs tobe periodically refreshed—generally involving a read and write operationevery 64 mS. Conventionally, the entire DRAM array is blindly refreshedeven though much of the memory may not be active. Conventional refreshoperations can consume as much as a third of the power consumptionassociated with the memory.

While DRAMs traditionally employ hardware-based refresh operations atvery high rates, a variety of other memory technologies provide fastaccess times similar to DRAM, but with much slower refresh raterequirements. For example, some forms of RRAM can operate with refreshrates on the order of seconds. Slower refresh rates can also bebeneficial for memory technologies that are susceptible to repetitivewrite operations that can degrade cell retention.

Thus, the need exists for an improved refresh scheme for memory systemsthat can minimize power dissipation and take advantage of reduced-raterefresh requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the disclosure are illustrated by way of example, and notby way of limitation, in the figures of the accompanying drawings and inwhich like reference numerals refer to similar elements and in which:

FIG. 1 illustrates a block diagram representing how conventionaloperating system software tracks active memory usage in a memory;

FIG. 2 illustrates a block diagram of a memory refresh system accordingto one embodiment;

FIG. 3 illustrates a high-level process flow of the system of FIG. 2;

FIG. 4 illustrates further details of the software and hardwareidentified in the system of FIG. 2;

FIG. 5 illustrates a flowchart identifying steps employed in oneembodiment of an allocated page tracking flow for the allocated pagelist of FIG. 4;

FIG. 6 illustrates a flowchart of steps representing one embodiment of anew page allocation process flow for the page table of FIG. 4;

FIG. 7 illustrates a method of generating refresh instructions andcorresponding refresh commands;

FIG. 8 illustrates a block diagram of one embodiment of a self-refreshcircuit for the memory device of FIG. 2; and

FIG. 9 illustrates a high-level process flow for the self-refreshcircuit of FIG. 8.

DETAILED DESCRIPTION

Embodiments of methods and apparatus for refreshing a memory aredisclosed. In one embodiment, a method of refreshing a memory includesaccessing from active memory an active memory map. The active memory mapis generated by software and identifies addresses corresponding to theactive memory and associated refresh criteria for the addresses. Therefresh criteria are evaluated for a portion of the active memory, andan operation initiated to refresh a portion of the active memory isbased on the refresh criteria. In this manner, low-power selectiverefresh operations may be successfully carried out by a software-basedrefresh scheme.

In a further embodiment, a method of managing memory refresh operationsis disclosed. The method involves a first mode of operation thatincludes generating an active memory map of the memory with software.The active memory map has addresses corresponding to active memoryallocated by the software, and is stored in a location within the activememory. The stored active memory map is accessed to evaluate refreshcriteria for a portion of the active memory. Based on the refreshcriteria, an operation to refresh a portion of the active memory isinitiated. Other embodiments include a self-refresh mode of operation inaddition to the first mode of operation where externally generatedrefresh instructions are not issued to refresh the memory.

Another embodiment presented herein relates to a memory device thatincludes storage cells operable to store an active memory map. Softwaregenerates the active memory map which identifies addresses of activememory in the memory device. In a first refresh mode of operation, thestorage cells are operable, in response to refresh commands based onoperations initiated by the software, to selectively refresh a portionof the active memory corresponding to the active memory map. In a secondmode of operation, the storage cells are operable, in response toself-refresh commands, to selectively refresh a portion of the activememory corresponding to a loaded bitmap version of the active memorymap.

In yet a further embodiment, a memory controller is disclosed thatincludes a host interface, decoder circuitry, and a memory interface.The host interface is operable to receive refresh instructions that arebased on an active memory map of a memory. The active memory map beinggenerated by operating system software under control of a host device.The decoder circuitry generates memory device address-specified refreshcommand signals based on the refresh instructions. The memory interfaceissues the refresh command signals to the memory to carry out selectiverefresh operations based on the active memory map.

FIG. 1 illustrates a block diagram representing a memory managementscheme, generally designated 100, that is often employed by moderncomputing systems to manage system memory. A total system memory mayinvolve a combination of virtual and physical memory. The physicalmemory is generally in the form of a main memory 102, and occasionallysupplemented virtually through interaction with a bulk memory 104.Moreover, a system's main memory 102 is often not fully allocated duringsystem operation.

To address the various possible memory configurations, a software-basedmemory manager is often used to monitor and map how the physical memoryis allocated within the computing system's total memory. The portion ofthe system memory realized by the main memory 102 usually includes aquickly accessible collection of volatile memory devices, while the bulkmemory 104 often takes the form of a hard disc 104 or other mass mediastorage device.

Further referring to FIG. 1, operating system software 106 manages theuse of the main memory 102 and tracks various statistics and otherinformation associated with the main memory 102. The allocated memory iscommonly referred to herein as “active memory.” Other informationtracked by the operating system software 106 includes the type of mainmemory in the system (such as a specific form of DRAM, flash, or othermemory technology), the active memory capacity, and other parameters.The system memory information is organized into page tables, such as afree page table 108 and an allocated page table 110. A “page” is a unitof memory from the perspective of the operating system software. Thepage table information is stored in the main memory 102 during systemoperation and is retrievable upon request from the operating systemsoftware or other application or process.

Referring now to FIG. 2, a computing system, generally designated 200,is shown that employs a unique refresh method for memory used in a mainmemory 204 by accessing allocated page table information such as thatnoted above with respect to FIG. 1. The system 200 generally includes ahost device 202, such as a general purpose processor coupled to thesystem main memory 204 via a system bus 205. Bulk memory 206 in the formof a hard disc interfaces with the host 202 as is well-known in the art.

Further referring to FIG. 2, operating system (OS) software 212generally manages the hardware resources of the computing system 200. Inone embodiment, the operating system software 212 generates andmaintains an allocated page table 214 that identifies the allocatedmemory, or “active memory”, in the main memory 204. The allocated pagetable 214 thus serves as a mapping of the physical memory actually usedduring system operation. With this information readily accessible,low-power refresh operations to selectively refresh only the allocatedmain memory may be realized.

With continued reference to FIG. 2, the main memory 204 includes amemory controller 208 that interfaces with a memory array 210. Thememory controller 208 may be realized as a discrete integrated circuit(IC), or formed on the host 202 as an on-chip controller, or packagedwith the memory array 210 in a system-in-package (SIP) configuration. Arefresh instruction decoder 216 is included in the memory controller 208to decode refresh instructions received from the host 202, and generateand issue corresponding refresh commands to the memory array 210 along acommand path 211, as more fully described below.

The memory array 210 in one embodiment takes the form of one or moreintegrated circuit memory devices. Data associated with the allocatedpage table 214 is stored in a portion of the memory array 210 as anactive memory map 216. The memory devices are formed in accordance withmemory cell technology that provides storage cells which exhibitrelatively long retention times. In specific embodiments, the retentiontimes are at least 650 ms. More generally, the retention time is of aduration longer than a time interval necessary to allow the operatingsystem software 212 to issue refresh instructions to the memorycontroller 208 to subsequently issue refresh commands to the memorydevices to refresh the active memory in the memory array 210 based onthe retrieved map.

In addition to allowing for refresh operations managed by the externaloperating system software 212, each memory device includes self-refreshhardware 218, explained in further detail below, to allow each memorydevice to enter and exit a low-power self-refresh mode of operation.When this mode is initiated, information based on the active memory map216 is bitmapped into bitmap portions of each device for access by eachmemory device during self-refresh. Selective self-refresh operations arethen enabled to refresh only those portions of active memory in eachmemory device, as mapped by the bitmapping. Further details regardingthis mode of operation are explained in the text that follows.

In operation, the system 200 of FIG. 2 carries out steps consistent withthe flowchart illustrated in FIG. 3 to selectively refresh only theportion of system memory that is “active” or allocated as indicated bythe active memory map 216 that is managed by the operating systemsoftware 212. At a high-level, the steps involve various softwarefunctions 301, such as those identified by steps 302-308, and hardwarefunctions 303 carried out by steps 310, 312, 314, 316 and 318. Further,multiple modes of operation are provided as noted above, relating toboth a standard refresh mode 305 set forth in steps 302, 304, 306, 308,310, 312, and a self-refresh mode 307 set forth in steps 316 and 318.

Referring to FIG. 3, at system start-up or initialization, the operatingsystem software 212 determines the system memory parameters, andidentifies “pages” of the main memory 210 that will be “active.” Asnoted above, a “page” is a quantity of memory from the perspective ofthe operating system software 212, and not to be confused with aphysical page (or row) of a memory device in the memory array 210.Information pertaining to the “active memory” is mapped to the physicalmemory space, at step 302, and stored in a portion of the memory array210 as the active memory map 216, at step 304.

Further referring to FIG. 3, refreshing the memory array 210 during thestandard refresh mode of operation 305 involves accessing the storedactive memory map 216 to manage refresh operations, at step 306. Moredetails relating to this step are explained below. Once the activememory map 216 is accessed (essentially the allocated page tableinformation), the operating system software 212 determines locations ofactive memory that need to be refreshed during a given time interval,and issues refresh instructions to the memory controller 208 to refreshonly the active memory corresponding to the active memory map 216, atstep 308. Up to this point, steps 302-308 are managed by the operatingsystem software 212 for the standard refresh mode of operation 305.Generally, at least one refresh instruction is generated by one maptable access. The table is sorted in time order of the pages, and thetable might be accessed multiple times until all refresh instructions ofthe pages reaching the refresh deadline are issued.

With continued reference to FIG. 3, the memory controller 208 receivesthe refresh instructions issued by the operating system software 212 anddecodes the instructions into address-specified refresh commands thatthe memory array 210 can respond to, at step 310. The refresh commandsare sent to the memory array 210 along the command path 211, and theaddress-specified portions of the memory array 210 are refreshed inresponse to the commands, at step 312. As noted above, the refreshcommands involve appropriate memory requests that generally read thecontents of the active memory, and re-write the contents back into thememory. Since only the portions of the memory array 210 that areactually allocated, or “active”, are refreshed, power dissipationassociated with refresh operations may be significantly reduced.

Following the refresh operation, the operating system software 212determines whether the self-refresh mode 307 should be initiated basedon predetermined self-refresh criteria, at step 314. If the self-refreshmode 307 is not initiated, then the next standard refresh operationbegins with a subsequent access of the active memory map 216 at step306. If the self-refresh mode 307 is initiated, at step 314, then theactive memory map 216 is copied to a portion of each memory device, atstep 316, and a hardware-based self-refresh scheme employed. In oneembodiment, this includes, for example, a state machine on each memorydevice to selectively refresh the portion of the memory array 210corresponding to the loaded memory map, at step 318.

FIGS. 4-9 illustrate further details relating to various embodimentsthat are consistent with the system and method set forth above withrespect to FIGS. 2 and 3. FIG. 4 illustrates further details pertainingto the software-to-hardware relationship between the operating systemsoftware 212 and the main memory 204. An allocated page list 402 isshown that identifies active memory by providing a first column 404 ofallocated page addresses PAGE ADDRESS0-PAGE ADDRESS5 and a second column406 that lists a refresh status parameter associated with each pageaddress. In one embodiment, the refresh status parameter for eachallocated page is a value generated by a decrementing timer thatrepresents a remaining retention time or “time to live” (TTL) of thecorresponding allocated page address. In a further specific embodiment,the allocated page addresses are sorted such that the allocated pageaddress associated with the lowest count is the highest priority entryin the page list, and all subsequent times corresponding to otherallocated pages are referenced to that count. For a current page, theTTL is the difference between a retention deadline information (RDI)value, and the TTL from the most recent previous page. This has abenefit of reducing map table checking overhead since it only needs tocheck the first page of the list.

Once the highest priority entry in the allocated page list 402decrements its refresh status count to zero (or some other predeterminedthreshold), a refresh manager 408 detects the condition and generatesrefresh instructions for the allocated page in terms of its virtualmemory space. The instructions are sent to a memory controller 410 (suchas the controller corresponding to the memory controller 208 in FIG. 2)via a refresh instruction path 412. In order to determine the refreshstatus times, the operating system software obtains the retentiondeadline information (RDI) associated with one or more memory devices414 at system boot-up from a control register 416 disposed on the memorycontroller 410. The memory controller 410 receives the instructions andutilizes a decoder 418 to translate the software-generated instructionsthat are in terms of physical memory into command signals in terms ofphysical memory and appropriate for memory device control. The commandsare then distributed to the various memory devices 414 to refresh thoseportions of active memory, such as at 420 a-420 d corresponding to theOS-identified allocated page needing refresh.

FIG. 5 illustrates an allocated page tracking method in accordance withone embodiment consistent with the software-to-hardware configurationdescribed with respect to FIG. 4. As noted above, in one embodiment, thepages identified in the allocated page list are sorted in order of thepage having the lowest “time to live” (TTL) count. Once the highestpriority page is sorted and identified, it is tracked, at step 502. TheTTL count for the sorted first page is then decremented in response to aperiodic timing reference, such as a system clock, at step 504. Adetermination is then made regarding the count value, at step 506. Ifthe count is above “0” or some other given threshold, then the softwarewaits for the next page tracking operation, at step 508. If it is nottime for a next page tracking operation, at step 510, the processcontinues to wait, at 508. The wait state will continue until a signalindicating the next page tracking operation is detected, at step 510.When the next page tracking operation is detected, the page trackingmethod reverts back to tracking a newly sorted highest priority page, atstep 502.

Further referring to FIG. 5, if the count reaches “0”, or some otherdesignated threshold when evaluated at step 506, the refresh manager 408schedules a refresh instruction for the page, at step 512. Once therefresh instruction is scheduled, the next-highest page is then treatedas the highest-priority page, and the scheduled page retention count isset relative to the previous pages retention count, at 514. In thismanner, the current page's TTL equals the RDI value minus the TTL of theprevious page. The allocated page address is then re-sorted to the endof the allocated page list 402, at 516.

In many situations, the operating system software 212 will update thesystem memory usage such that new pages may be added to allocatedmemory. FIG. 6 illustrates a flowchart identifying steps for a method ofallocating new pages to the allocated page list 402 (FIG. 4). The methodinvolves first allocating a new page entry to the allocated page list402, at 602. Information concerning the new page is then received fromthe free page list 108 (FIG. 1) in the operating system software, atstep 604, and removed from the free page list 108, at 606. The newallocated page is then linked to the end of the allocated page list 402,at 608. If the new allocated page is the only allocated page, at 610,then the new allocated page's time to live count TTL is set to match theretention deadline information (RDI) retrieved at system boot-up. If thenew page is not the only allocated page, then the allocated page TTLvalue is set to a difference between the retention deadline informationRDI and the previous page TTL value, at step 612.

FIG. 7 illustrates further detail relating to one embodiment of a methodof generating refresh instructions by the refresh manager 408 (FIG. 4),and decoding the OS-generated refresh instructions by the memorycontroller decoder 418. As a given refresh operation corresponding to apage of memory is scheduled, at step 702, the operating system softwaregenerates a refresh instruction for the page, at step 704. As shown inthe blowup detail at 706, the information or “page mapping” associatedwith one embodiment of a refresh instruction includes a physical memorypage address 708 that includes a row address 710 and a column offsetaddress 712. A page offset 714 is also identified, including bankinformation 716, rank, channel and DIMM information 718, and a blockoffset value 720. Once the refresh instruction is generated by therefresh manager 408, it is dispatched to the memory controller 410.

Further referring to FIG. 7, the memory controller 410 receives therefresh instruction, at step 722, and decodes the instruction into oneor more refresh commands, at step 724. As shown in the blowup detail at726, one specific embodiment involves decoding each OS page refreshinstruction into eight refresh commands. Each command includesinformation relating to chip select values 728, a bank select value 730and row select value 732. Eight exemplary commands are showncorresponding to the basic command structure.

Once the memory commands are generated, the memory controller 410schedules the commands into appropriate queues and issues the commandsto the one or more memory devices 414 corresponding to the page, at step710. The addressed portions of the one or more memory devices are thenrefreshed in response to the commands, at step 712. Should the systeminitiate a self-refresh mode of operation, further refresh instructionsinitiated by the operating system software are halted, and instead,refresh activities are carried out solely on the memory devices 414 asmore fully described with respect to FIGS. 8 and 9.

Referring now to FIG. 8, each memory device 414 in the main memoryincludes self-refresh hardware 802 that allows each memory device 414 tocarry out refresh operations internally without external commands fromoutside the device. Generally, self-refresh is employed as a low-powermode of operation for each memory device to enable each device to retainits stored information while a system clock is shut down. This, inessence, puts the memory device 414 into a “sleep” mode. Selectiverefresh of only the portions of the memory device 414 that are active orallocated thus provides even further power saving benefits over andabove just shutting down the system clock.

In one embodiment, the refresh hardware 802 interfaces with a bitmapportion 804 of each memory device 414. The bitmap portion stores abitmap representation of the active memory map (such as 216, FIG. 2)used in the standard refresh mode. One specific embodiment employs onebitmap per bank 805, with each row (such as 806 a-806 c) of the bankrepresented by a single bit in the bitmap 804. The state of each bitindicates whether or not the corresponding row has been allocated tosystem memory or “active.” Thus, for a bank of 16K rows, a suitablebitmap has a size of 16K bits. In other embodiments, instead of loadinginformation representing the active memory map into a bitmap portion ofthe device, storage locations such as the active memory itself, or tagmemory coupled to the active memory within the memory device 414 may beloaded with information corresponding to the active memory map.

Further referring to FIG. 8, the self-refresh hardware 802 takes theform of a state machine that includes a self-refresh management engine804 that interfaces with a variety of counters to control theself-refresh operations. The counters include a timer counter TC, arefresh address counter RAC, a bitmap counter BMC and a bitmap indexcounter BIC. The timer counter TC generally tracks the refresh intervaltime while the refresh address counter RAC increments through the bankrow addresses for refreshing. The bitmap counter BMC provides a bitmapof a set number of rows, such as sixty-four, to self-refresh and duringoperation is compared against the refresh address counter RAC when thetimer counter TC expires to determine whether a refresh is needed. Thebitmap index counter BIC provides an address index of the bitmap for asubsequent bitmap counter fetch, and in one embodiment provides 8 bitsfor 16K rows.

FIG. 9 illustrates a high-level process flow for a self-refresh methodthat utilizes the self-refresh hardware 802 of FIG. 8. Once thecomputing system initiates a self-refresh mode of operation, at step902, a bitmap version of the active memory map 216 stored in activememory is loaded to the bitmap blocks 804 of the memory devicesundergoing self-refresh, at step 904. The memory device state machinehardware then traverses the bitmap information and refreshes the rowsthat have a corresponding bit in the bitmap indicating the row'sallocation in active memory. With the bitmap index counter BIC keepingtrack of the row and column addresses of where the state machine is atwith respect to refreshing the memory device rows, the bitmap counterBMC periodically fetches a block of 64 rows (a subset of the bitmap) forrefreshing every interval of n cycles. The interval is based on thetimer counter TC and the number of rows in the block to be refreshed.When the system exits the self-refresh mode of operation, the operatingsystem software 212 regains control over the memory refresh operationsas described above with respect to the standard refresh mode.

Those skilled in the art will appreciate the benefits and advantagesafforded by the embodiments described herein. Selectively refreshingonly those memory locations that are allocated to active memory providessignificant power savings due to reductions in refresh current.Moreover, handling selective refresh via a software-based scheme thattracks the allocated memory reduces implementation costs and complexity.By providing ways to selectively refresh active memory in both standardand self-refresh modes, further power savings may be realized.

When received within a computer system via one or more computer-readablemedia, such data and/or instruction-based expressions of the abovedescribed circuits may be processed by a processing entity (e.g., one ormore processors) within the computer system in conjunction withexecution of one or more other computer programs including, withoutlimitation, net-list generation programs, place and route programs andthe like, to generate a representation or image of a physicalmanifestation of such circuits. Such representation or image maythereafter be used in device fabrication, for example, by enablinggeneration of one or more masks that are used to form various componentsof the circuits in a device fabrication process.

In the foregoing description and in the accompanying drawings, specificterminology and drawing symbols have been set forth to provide athorough understanding of the present invention. In some instances, theterminology and symbols may imply specific details that are not requiredto practice the invention. For example, any of the specific numbers ofbits, signal path widths, signaling or operating frequencies, componentcircuits or devices and the like may be different from those describedabove in alternative embodiments. Also, the interconnection betweencircuit elements or circuit blocks shown or described as multi-conductorsignal links may alternatively be single-conductor signal links, andsingle conductor signal links may alternatively be multi-conductorsignal links. Signals and signaling paths shown or described as beingsingle-ended may also be differential, and vice-versa. Similarly,signals described or depicted as having active-high or active-low logiclevels may have opposite logic levels in alternative embodiments.Component circuitry within integrated circuit devices may be implementedusing metal oxide semiconductor (MOS) technology, bipolar technology orany other technology in which logical and analog circuits may beimplemented. With respect to terminology, a signal is said to be“asserted” when the signal is driven to a low or high logic state (orcharged to a high logic state or discharged to a low logic state) toindicate a particular condition. Conversely, a signal is said to be“deasserted” to indicate that the signal is driven (or charged ordischarged) to a state other than the asserted state (including a highor low logic state, or the floating state that may occur when the signaldriving circuit is transitioned to a high impedance condition, such asan open drain or open collector condition). A signal driving circuit issaid to “output” a signal to a signal receiving circuit when the signaldriving circuit asserts (or deasserts, if explicitly stated or indicatedby context) the signal on a signal line coupled between the signaldriving and signal receiving circuits. A signal line is said to be“activated” when a signal is asserted on the signal line, and“deactivated” when the signal is deasserted. Additionally, the prefixsymbol “/” attached to signal names indicates that the signal is anactive low signal (i.e., the asserted state is a logic low state). Aline over a signal name (e.g., ‘<signal name>’) is also used to indicatean active low signal. The term “coupled” is used herein to express adirect connection as well as a connection through one or moreintervening circuits or structures. Integrated circuit device“programming” may include, for example and without limitation, loading acontrol value into a register or other storage circuit within the devicein response to a host instruction and thus controlling an operationalaspect of the device, establishing a device configuration or controllingan operational aspect of the device through a one-time programmingoperation (e.g., blowing fuses within a configuration circuit duringdevice production), and/or connecting one or more selected pins or othercontact structures of the device to reference voltage lines (alsoreferred to as strapping) to establish a particular device configurationor operation aspect of the device. The term “exemplary” is used toexpress an example, not a preference or requirement.

While the invention has been described with reference to specificembodiments thereof, it will be evident that various modifications andchanges may be made thereto without departing from the broader spiritand scope of the invention. For example, features or aspects of any ofthe embodiments may be applied, at least where practicable, incombination with any other of the embodiments or in place of counterpartfeatures or aspects thereof. Accordingly, the specification and drawingsare to be regarded in an illustrative rather than a restrictive sense.

What is claimed is:
 1. (canceled)
 2. A method of refreshing allocatedportions of a memory, the method comprising: sorting the allocatedportions to determine a highest priority portion of the allocatedportions, the sorting based on a refresh status parameter associatedwith the allocated portions; tracking the refresh status parameter ofthe highest priority portion; and scheduling a refresh instruction forthe highest priority portion based on the tracked refresh statusparameter reaching a threshold value.
 3. The method of claim 2, wherein:the allocated portions each represent a page of memory storage locationscorresponding to a page address.
 4. The method of claim 2, wherein: therefresh status parameter associated with the highest priority portioncomprises a count value representing expiration of a retention timeassociated with the highest priority portion.
 5. The method of claim 4,wherein the tracking comprises: initiating a page operation;decrementing the count value in response to the initiating; determiningwhether the decremented count reaches the threshold value; anditeratively repeating the initiating, decrementing and determining untilthe count reaches the threshold.
 6. The method of claim 2 whereinsorting and tracking are carried out by operating system software. 7.The method of claim 2 wherein the scheduling is carried out by operatingsystem software.
 8. The method of claim 2, further comprising: afterscheduling the refresh instruction, sorting the highest priority portionas a lowest priority portion.
 9. A method, comprising: prioritizingrefresh operations for a memory device, the prioritizing includingidentifying active portions of the memory device as allocated portions;associating the allocated portions with a refresh status parameter;sorting the allocated portions to determine a highest priority portionof the allocated portions, the sorting based on the refresh statusparameter associated with the allocated portions; tracking the refreshstatus parameter of the highest priority portion; and scheduling arefresh instruction for the highest priority portion based on thetracked refresh status parameter reaching a threshold value.
 10. Themethod of claim 9 wherein: the allocated portions each represent a pageof memory storage locations corresponding to a page address.
 11. Themethod of claim 9, wherein: the refresh status parameter associated withthe highest priority portion comprises a count value representingexpiration of a retention time associated with the highest priorityportion.
 12. The method of claim 11, wherein the tracking comprises:initiating a page operation; decrementing the count value in response tothe initiating; determining whether the decremented count reaches thethreshold value; and iteratively repeating the initiating, decrementingand determining until the count reaches the threshold.
 13. The method ofclaim 9 wherein sorting and tracking are carried out by operating systemsoftware.
 14. The method of claim 9 wherein the scheduling is carriedout by operating system software.
 15. The method of claim 9, furthercomprising: after scheduling the refresh instruction, sorting thehighest priority portion as a lowest priority portion.
 16. A refreshcontroller for prioritizing refresh operations for allocated portions ofa memory, the refresh controller comprising: a tracking module includinga sorter to sort the allocated portions to determine a highest priorityportion of the allocated portions, the sort based on a refresh statusparameter associated with the allocated portions, and a tracker to trackthe refresh status parameter of the highest priority portion; and arefresh manager in communication with the tracker to schedule a refreshinstruction for the highest priority portion based on the trackedrefresh status parameter reaching a threshold value.
 17. The refreshcontroller of claim 16, wherein: the allocated portions each represent apage of memory storage locations corresponding to a page address. 18.The refresh controller of claim 16, wherein: the refresh statusparameter associated with the highest priority portion comprises a countvalue representing expiration of a retention time associated with thehighest priority portion.
 19. The refresh controller of claim 18,wherein: the tracker is operative to initiate a page operation;decrement the count value in response to the initiating; determinewhether the decremented count reaches the threshold value; anditeratively repeat the initiate, decrement and determine until the countreaches the threshold.
 20. The refresh controller of claim 16, wherein:the sorter and the tracker are controlled by operating system software.21. The method of claim 16 wherein: the refresh manager is controlled byoperating system software.